In deep sub-micron integrated circuit (IC) technology, an embedded static random access memory (SRAM) device has become a popular storage unit of high speed communication, image processing and system-on-chip (SOC) products. For example, a dual port (DP) SRAM device allows parallel operation, such as 1R (read) 1W (write), or 2R (read) in one cycle, and therefore has higher bandwidth than a single port SRAM. In advanced technologies with decreased feature size and increased packing density, low loading and high speed of the cell structure are important factors in embedded memory and SOC products.
As lithography methods used in IC fabrication continually improve to allow smaller and smaller feature sizes to be created in metal and semiconductor features, the pitch (i.e., the center-to-center or edge-to-edge distance) between features continually decreases. In advanced process nodes such as 10 nm or below, restricted design rules in layout are adopted for extending the capabilities of existing lithography tools, such as 193-nm immersion lithography. These restrictions include uni-directional routing and fixed (i.e., uniform) pitch between metal lines. The uni-directional routing rule for metal lines in conjunction with the fixed pitch routing rule may create situations where metal lines cannot be properly aligned between adjoining regions of a chip that are not subject to the same routing rules, e.g., between an SRAM cell region and a peripheral logic region, therefore preventing electrical connection between the two chip regions. Improvements in these areas are desired.